Amandeep Singh

Amandeep Singh

Senior Research Fellow @ IIT Roorkee

PhD in Electronics and Communication Engineering

SRAM Memory Design In-Memory Computation VLSI Design Engineer

About Me

๐—ฃ๐—ต๐—— ๐—ฅ๐—ฒ๐˜€๐—ฒ๐—ฎ๐—ฟ๐—ฐ๐—ต ๐—™๐—ผ๐—ฐ๐˜‚๐˜€

I am a PhD researcher at IIT Roorkee, specializing in the design and hardware validation of high-performance In-Memory Computing (IMC) architectures for energy-efficient AI acceleration.

๐—ฃ๐—ต๐—— ๐—ฆ๐˜‚๐—ฝ๐—ฒ๐—ฟ๐˜ƒ๐—ถ๐˜€๐—ผ๐—ฟ

I am privileged to be working under the guidance of Prof. Bishnu Prasad Das.

๐—ง๐—ฒ๐—ฐ๐—ต๐—ป๐—ถ๐—ฐ๐—ฎ๐—น ๐—ฆ๐—ฝ๐—ฒ๐—ฐ๐—ถ๐—ฎ๐—น๐—ถ๐˜‡๐—ฎ๐˜๐—ถ๐—ผ๐—ป

My expertise includes developing time-domain computation techniques using specialized voltage-controlled and PVT-insensitive delay cells integrated with SRAM arrays to perform XAC and MAC operations, fundamental to BNN and CNN.

๐——๐—ฒ๐˜€๐—ถ๐—ด๐—ป ๐—š๐—ผ๐—ฎ๐—น๐˜€ & ๐—ฉ๐—ฒ๐—ฟ๐—ถ๐—ณ๐—ถ๐—ฐ๐—ฎ๐˜๐—ถ๐—ผ๐—ป

A core objective is to create IMC architectures that are linear, high-throughput, area-efficient, and energy-efficient. I verify performance using MNIST and CIFAR-10 datasets.

๐—™๐˜‚๐—น๐—น-๐—–๐—ต๐—ถ๐—ฝ ๐——๐—ฒ๐˜€๐—ถ๐—ด๐—ป ๐—˜๐˜…๐—ฝ๐—ฒ๐—ฟ๐˜๐—ถ๐˜€๐—ฒ

I possess end-to-end expertise across the entire VLSI design cycle, including architecture definition, custom circuit design, and full-chip physical implementation.

๐—ฆ๐—ถ๐—น๐—ถ๐—ฐ๐—ผ๐—ป-๐—ฃ๐—ฟ๐—ผ๐˜ƒ๐—ฒ๐—ป ๐—ฆ๐˜‚๐—ฐ๐—ฐ๐—ฒ๐˜€๐˜€

I have successfully led three silicon tapeouts in the TSMC 65 nm node for applications including neural networks (BNN and CNN) and the SHA-3 cryptographic algorithm.

BNN Accelerator CNN Accelerator SHA-3 Crypto

๐—ง๐—ฒ๐—ฐ๐—ต๐—ป๐—ถ๐—ฐ๐—ฎ๐—น ๐—ฃ๐—ฟ๐—ผ๐—ณ๐—ถ๐—ฐ๐—ถ๐—ฒ๐—ป๐—ฐ๐˜†

I am proficient with industry-standard EDA tools, frameworks, and languages, including:

Cadence Virtuoso Design Compiler IC Compiler PrimeTime (STA) HSPICE Xilinx Vivado FPGA Prototyping TensorFlow Verilog SystemVerilog VHDL TCL Python C++

๐—ฃ๐—ฟ๐—ฒ๐—บ๐—ถ๐—ฒ๐—ฟ ๐—”๐˜„๐—ฎ๐—ฟ๐—ฑ๐˜€

Recognized with the Best Digital IC Tapeout Award twice at the VLSID conference in 2025 and 2026.

VLSID 2025 VLSID 2026

๐—š๐—ฟ๐—ฎ๐—ป๐˜๐˜€ & ๐—™๐—ฒ๐—น๐—น๐—ผ๐˜„๐˜€๐—ต๐—ถ๐—ฝ๐˜€

Received grants from SERB and IEEE CAS for international travel, alongside multiple conference fellowships in India.

๐—ง๐—ฒ๐—ฎ๐—ฐ๐—ต๐—ถ๐—ป๐—ด & ๐— ๐—ฒ๐—ป๐˜๐—ผ๐—ฟ๐˜€๐—ต๐—ถ๐—ฝ

Contributed as a Teaching Assistant for Digital System Design on Coursera and transcribed courses for NPTEL.

๐—ฅ๐—ฒ๐˜€๐—ฒ๐—ฎ๐—ฟ๐—ฐ๐—ต ๐—ฃ๐˜‚๐—ฏ๐—น๐—ถ๐—ฐ๐—ฎ๐˜๐—ถ๐—ผ๐—ป๐˜€

I have authored three papers published in IEEE international conferences and journals, with an additional paper currently in queue and under review.

๐—œ๐—– ๐—ง๐—ฒ๐˜€๐˜๐—ถ๐—ป๐—ด ๐—Ÿ๐—ฎ๐—ฏ, ๐—œ๐—œ๐—ง ๐—ฅ๐—ผ๐—ผ๐—ฟ๐—ธ๐—ฒ๐—ฒ

Academic Details

Degree Institution Year CGPA/Percentage
Ph.D. Indian Institute of Technology, Roorkee 2026 8.429
M.Tech Punjab Engineering College (Deemed to Be University), Chandigarh 2020 8.740
B.Tech Guru Gobind Singh College of Modern Technology, Kharar 2014 82.60%
Class XII Central Public Senior Secondary School, Ghoman (PSEB) 2010 70.44%
Class X S.G.H.K. Public School, Ghoman (PSEB) 2008 72.70%

Research Projects

2024 TSMC 65nm

Time-Domain IMC Architecture

TD-IMC for XAC and Multibit MAC Operations

Introduced voltage-controlled delay cell (VCDC) for XNOR/MAC operations. No DAC/ADC required.

1711 GOPS 544 TOPS/W 99.22% MNIST
CadenceHSPICEVivado
2022-23 TSMC 65nm

PVT-Insensitive IMC

Binary Neural Networks Accelerator

XNOR-and-delay cell (XDC) with PVT-tolerant PXDC architecture. Improved linearity & signal margin.

1057 GOPS 673 TOPS/W 99.6% MNIST
CadenceHSPICEICC
2023 65nm

VCDC Ring Oscillator IMC

128x128 6T-SRAM Array

Ring oscillator based architecture. No DAC/ADC/TDC required. Serial/parallel row access.

1321 GOPS 49.5 TOPS/W 99% MNIST
CadenceVivadoDC
2020 180nm

Two-Stage Op-Amp

High Gain Amplifier Design

Designed two-stage operational amplifier with high gain and low power.

80.65 dB Gain 125 MHz UGB 251 ยตW
Cadence
2019-20 180nm

Low-Power Dynamic Comparator

Single-tail & Double-tail Analysis

Analyzed comparators for reduced delay and power dissipation.

11.49 ยตW 58.67 ns
Cadence
2014 Embedded

Embedded Quiz Game

C-DAC Mohali

AT89C51 microcontroller, 20x4 LCD, portable quiz system.

Embedded C8051
2025 TSMC 65nm

SHA-3 Hardware Accelerator

In-Memory Computation for Cryptography

5-input XOR, fused XOR-Rotation, RCS scheme. Under fabrication (May 2025).

500 MHz 192 Mbps 2388 cycles
CadenceHSPICEICC

Research Publications

PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks

A. Singh and B. P. Das

IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, 2024

doi: 10.1109/ISCAS58744.2024.10558168

A Configurable 10T SRAM-Based IMC Accelerator With Scaled-Voltage-Based Pulse Count Modulation for MAC and High-Throughput XAC

P. K. Saragada, S. Manna, A. Singh and B. P. Das

IEEE Transactions on Nanotechnology, 2023

doi: 10.1109/TNANO.2023.3269946

Area-Efficient In-Memory Computation with Improved Linearity using Voltage-Controlled Delay Cell-based Ring Oscillator

A. Singh and B. P. Das

IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad, 2023

doi: 10.1109/iSES58672.2023.000

Dual-VTH XDC-Based Time-Domain In-Memory Computing Architecture with PVT-Insensitive XAC Operations for BNN Applications

A. Singh and B. P. Das

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Submitted)

ID TVLSI-00772-2025

Technical Skills

Programming Languages

HSPICE Verilog SystemVerilog VHDL TCL Python C++

EDA Tools

Cadence Virtuoso Design Compiler IC Compiler PrimeTime (STA) HSPICE LTSpice Xilinx Vivado TensorFlow MATLAB

Additional Expertise

Digital VLSI Design FPGA Prototyping Semiconductor Memories Memory Design & Testing Machine Learning Analog VLSI Full-Chip Physical Design

Awards & Achievements

Best Digital IC Tapeout Award

VLSID 2025, Bengaluru

Best Digital IC Tapeout Award

VLSID 2026

SERB & IEEE CAS Grant

ISCAS 2024, Singapore

Teaching Assistant

Digital System Design (Coursera)

NPTEL Transcription

VLSI Physical Design With Timing Analysis

GATE 2019

Score 645 | AIR 1517

GATE 2018

Score 446 | AIR 4438

GATE 2017

Score 598 | AIR 2667

Conference Fellowships

Multiple VLSI Conferences

Positions & Activities

Technical Presenter

IEEE ISCAS 2024, Singapore - Presented research on PVT-Insensitive IMC

Technical Presenter

IEEE iSES 2023, Ahmedabad - Presented ring oscillator IMC architecture

Attendee

VLSI Design 2024 & 2021 Conferences

Workshop Presenter

IEEE CAS Workshop "Semiconductors for All", New Delhi 2024

Internship

Embedded System Intern

Centre for Development of Advanced Computing (C-DAC Mohali)

January 2014 - July 2014

Developed an embedded-based quiz game using AT89C51 microcontroller, 20x4 LCD, and 74573 MUX. Area-efficient, low power, portable design suitable for educational institutions.

Contact

Email

a_singh@ece.iitr.ac.in

Phone

+91 9501286656

Address

IIT Roorkee, Roorkee, Uttarakhand, India

Research Supervisor

Dr. Bishnu Prasad Das

Professor, Department of ECE

Indian Institute of Technology, Roorkee

bishnu.das@ece.iitr.ac.in

+91-1332-28479

Faculty Profile